#ifndef __SN32F288_KB_RF_H
#define __SN32F288_KB_RF_H


/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F280.h>
#include <SN32F200_Def.h>


/*_____ D E F I N I T I O N S ______________________________________________*/
#define		BK_MOSI_OUTPUT	SN_GPIO3->MODE_b.MODE6 = 1
#define		BK_MOSI_HIGH		SN_GPIO3->BSET_b.BSET6 = 1
#define		BK_MOSI_LOW			SN_GPIO3->BCLR_b.BCLR6 = 1

#define		BK_CLK_OUTPUT		SN_GPIO2->MODE_b.MODE15 = 1
#define		BK_CLK_HIGH			SN_GPIO2->BSET_b.BSET15 = 1
#define		BK_CLK_LOW			SN_GPIO2->BCLR_b.BCLR15 = 1

#define		BK_CS_OUTPUT		SN_GPIO0->MODE_b.MODE14 = 1
#define		BK_CS_HIGH			SN_GPIO0->BSET_b.BSET14 = 1
#define		BK_CS_LOW				SN_GPIO0->BCLR_b.BCLR14 = 1

#define		BK_CE_OUTPUT		SN_GPIO0->MODE_b.MODE15 = 1
#define		BK_CE_HIGH			SN_GPIO0->BSET_b.BSET15 = 1
#define		BK_CE_LOW				SN_GPIO0->BCLR_b.BCLR15 = 1

#define		BK_MISO_STATUS	SN_GPIO1->DATA_b.DATA9
/*_____ D E F I N I T I O N S ______________________________________________*/

//---------------------------------------------------------------------------------
//LT8900 REG Address(Write)
//---------------------------------------------------------------------------------
#define		W_REG0			0x00		//
#define		W_REG1			0X01		//
#define		W_REG2			0X02		//
#define		W_REG4			0X04		//
#define		W_REG5			0X05		//
#define		W_REG7			0X07		//
#define		W_REG8			0X08		//
#define		W_REG9			0X09		//
#define		W_REG10			0X0A		//
#define		W_REG11			0X0B		//
#define		W_REG12			0X0C		//
#define		W_REG13			0X0D		//
#define		W_REG22			0X16		//
#define		W_REG23			0X17		//
#define		W_REG24			0X18		//
#define		W_REG25			0X19		//
#define		W_REG26			0X1A		//	
#define		W_REG27			0X1B		//	
#define		W_REG28			0X1C		//
#define		W_REG29			0X1D		//
#define		W_REG30			0X1E		//
#define		W_REG31			0X1F		//
#define		W_REG32			0X20		//
#define		W_REG33			0X21		//
#define		W_REG34			0X22		//
#define		W_REG35			0X23		//
#define		W_REG36			0X24		//
#define		W_REG37			0X25		//
#define		W_REG38			0X26		//
#define		W_REG39			0X27		//
#define		W_REG40			0X28		//
#define		W_REG41			0X29		//
#define		W_REG42			0X2A		//
#define		W_REG43			0X2B		//
#define		W_REG44			0X2C		//
#define		W_REG45			0X2D		//
#define		W_REG50			0X32		//
#define		W_REG52			0X34		//
//------------------------------------------------------------------------------------
//LT8900 REG Address(Read)
//------------------------------------------------------------------------------------
#define		R_REG3			0X83		//
#define		R_REG6			0X86		//
#define		R_REG29			0X9D		//
#define		R_REG30			0X9E		//
#define		R_REG31			0X9F		//
#define		R_REG32			0XA0		//
#define		R_REG33			0XA1		//
#define		R_REG34			0XA2		//
#define		R_REG35			0XA3		//
#define		R_REG36			0XA4		//
#define		R_REG37			0XA5		//
#define		R_REG38			0XA6		//
#define		R_REG39			0XA7		//
#define		R_REG40			0XA8		//
#define		R_REG41			0XA9		//
#define		R_REG42			0XAA		//
#define		R_REG43			0XAB		//
#define		R_REG48			0XB0		//
#define		R_REG50			0XB2		//	
#define		R_REG52			0XB4		//
//---------------------------------------------------------------------------------
//LT8900 Write Data Define
//---------------------------------------------------------------------------------
#define		C_TX_ENB		0x01		//
#define		C_RX_ENB		0x80		//
#define		C_IDLE_ENB	0x00		//
#define		CLEAR_TX_FIFO_H	0x80		//
#define		CLEAR_TX_FIFO_L	0x00		//
#define		CLEAR_RX_FIFO_H	0x00		//
#define		CLEAR_RX_FIFO_L	0x80		//
#define		RF_FRE_BASE	0x23		//
#define		RF_TX_LEN		32		//
#define		RF_RX_LEN		0x05		//	
//---------------------------------------------------------------------------------
//SYNC Define
//---------------------------------------------------------------------------------
#define		C_SYNC_36ADD_L	0xD5		//
#define		C_SYNC_36ADD_H	0x42		//
#define		C_SYNC_38ADD_L	0x12		//
#define		C_SYNC_38ADD_H	0x33		//		
#define		C_SYNC_39ADD_L	0x25		//
#define		C_SYNC_39ADD_H	0x15		//

#define		C_SYNC_NOR_36ADD_L	0xA6
#define		C_SYNC_NOR_36ADD_H	0x95
#define		C_SYNC_NOR_39ADD_L	0xD5		//


//************************FSK COMMAND and REGISTER****************************************//
// SPI(BK2425) commands
#define READ_REG        0x00  // Define read command to register
#define WRITE_REG       0x20  // Define write command to register
#define RD_RX_PLOAD     0x61  // Define RX payload register address
#define WR_TX_PLOAD     0xA0  // Define TX payload register address
#define FLUSH_TX        0xE1  // Define flush TX register command
#define FLUSH_RX        0xE2  // Define flush RX register command
#define REUSE_TX_PL     0xE3  // Define reuse TX payload register command
#define W_TX_PAYLOAD_NOACK_CMD	0xb0
#define W_ACK_PAYLOAD_CMD	0xa8
#define ACTIVATE_CMD		0x50
#define R_RX_PL_WID_CMD		0x60
#define NOP             0xFF  // Define No Operation, might be used to read status register

// SPI(BK2425) registers(addresses)
#define CONFIG          0x00  // 'Config' register address
#define EN_AA           0x01  // 'Enable Auto Acknowledgment' register address
#define EN_RXADDR       0x02  // 'Enabled RX addresses' register address
#define SETUP_AW        0x03  // 'Setup address width' register address
#define SETUP_RETR      0x04  // 'Setup Auto. Retrans' register address
#define RF_CH           0x05  // 'RF channel' register address
#define RF_SETUP        0x06  // 'RF setup' register address
#define STATUS          0x07  // 'Status' register address
#define OBSERVE_TX      0x08  // 'Observe TX' register address
#define CD              0x09  // 'Carrier Detect' register address
#define RX_ADDR_P0      0x0A  // 'RX address pipe0' register address
#define RX_ADDR_P1      0x0B  // 'RX address pipe1' register address
#define RX_ADDR_P2      0x0C  // 'RX address pipe2' register address
#define RX_ADDR_P3      0x0D  // 'RX address pipe3' register address
#define RX_ADDR_P4      0x0E  // 'RX address pipe4' register address
#define RX_ADDR_P5      0x0F  // 'RX address pipe5' register address
#define TX_ADDR         0x10  // 'TX address' register address
#define RX_PW_P0        0x11  // 'RX payload width, pipe0' register address
#define RX_PW_P1        0x12  // 'RX payload width, pipe1' register address
#define RX_PW_P2        0x13  // 'RX payload width, pipe2' register address
#define RX_PW_P3        0x14  // 'RX payload width, pipe3' register address
#define RX_PW_P4        0x15  // 'RX payload width, pipe4' register address
#define RX_PW_P5        0x16  // 'RX payload width, pipe5' register address
#define FIFO_STATUS     0x17  // 'FIFO Status Register' register address
#define	RF_FEATURE			0x1D
#define PAYLOAD_WIDTH   0x1f  // 'payload length of 256 bytes modes register address

#define POWER_VALUE_5DBM                        5
#define POWER_VALUE_0DBM                        4
#define POWER_VALUE_MINUS_5DBM                  3
#define POWER_VALUE_MINUS_10DBM                 2
#define POWER_VALUE_MINUS_15DBM                 1
#define POWER_VALUE_MINUS_20DBM                 0

//interrupt status
#define STATUS_RX_DR 0x40
#define STATUS_TX_DS 0x20
#define STATUS_MAX_RT 0x10

#define STATUS_TX_FULL 0x01

//FIFO_STATUS
#define FIFO_STATUS_TX_REUSE 0x40
#define FIFO_STATUS_TX_FULL 0x20
#define FIFO_STATUS_TX_EMPTY 0x10

#define FIFO_STATUS_RX_FULL 0x02
#define FIFO_STATUS_RX_EMPTY 0x01


#define	RF_POWERON			0x01
#define	RF_POWERDOWN		0x00

/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint16_t rResend_Cnt;
extern uint8_t rRF_ID1,rRF_ID2,rRF_ID3;
extern uint8_t bmRSSI_Flag;
#define		RF_RESEND1_TIME			8			//8ms@1ms
#define		RF_RESEND2_TIME			1			//1ms@1ms

extern uint8_t f_Automode_En;
extern uint8_t f_RF_PairSend;
extern uint8_t f_RF_LEDReq;
extern uint8_t RF_Send_Length;
extern uint8_t RF_Rx_Length;
extern uint8_t RF_PipeNo;
extern uint8_t f_RF_check;
extern uint8_t r_IndicLED_Cnt;
extern uint8_t bmSendLinkFlag;
extern uint8_t r_PairSend_Cnt;
extern uint8_t r_IndicLED_Cnt;
extern uint8_t f_RF_LED;
#define		PAIR_SEND_CNT				5			//10ms@2ms

#define		RF_IDLE_CNT					50		//100ms@2ms
#define		INDIC_LED_LCNT			100		//200ms@2ms
#define		INDIC_LED_CNT				10		//20ms@2ms

#define		RF_LVD_VOL_L						2123		//(3.3*499/(499+560)*4096/3)
#define		RF_LVD_VOL_H						2445		//(3.8*499/(499+560)*4096/3)		

void RF_channel_switch(void);

void SPI_Write_Reg(uint8_t reg, uint8_t value);
uint8_t SPI_Read_Reg(uint8_t reg);
void SwitchCFG(char _cfg);
void BK_RD_NByte(uint8_t reg,uint32_t len);
void BK_WT_NByte(uint8_t reg,uint8_t *pData,uint32_t len);
void BK_Send_Package(uint8_t cmd,uint8_t *pData,uint32_t len);
void SwitchToRxMode(void);
void SwitchToTxMode(void);
void SwitchToIdleMode(void);
void RF_PowerMode(uint8_t power);
void RF_IndicLED_Send_Chat(void);
void RF_Pair_Send_Chat(void);
void RF_ReSend_Check(void);
void RF_KeyRelease_Chat(void);

extern const uint8_t RF_CHANNEL_TABLE[];
extern const uint32_t Bank1_Reg0_13[];
extern uint8_t Bank1_Reg14[];
extern const uint8_t Bank0_Reg[][2];
extern const uint8_t Bank0_Reg_Len;
extern uint8_t RX0_Address[];
extern uint8_t RX1_Address[];
extern uint8_t Bank1_SingleCarrier_Reg4[];

void driver_rf_ouput_power_value_set(uint8_t power);
void driver_rf_spi_write_bank1_reg(uint8_t reg, uint32_t value);
void RF_Resend_Chat(void);
uint8_t RF_Send_NTime(void);
void RF_Send_OneTime(void);
void RF_Payload_Clear(void);
void BK_Init(void);
void RF_Work(void);
void RF_PairMode_Set(void);
void RF_Pair_Set(void);
void RF_Set_Commun_SyncWord(void);
void RF_Set_Default_SyncWord(void);
uint8_t Chk_CRC(void);
void RF_RSSI_Mode(void);
void KB_RFParam_Flash(void);
void KB_RFParam_Reset(void);
#endif	/*__SN32F288_KB_RF_H*/
